Analysis and identification of possible automation approaches for embedded systems design flows

Sophisticated and high performance embedded systems are present in an increasing number of application domains. In this context, formal-based design methods have been studied to make the development process robust and scalable. Models of computation (MoC) allows the modeling of an application at a high abstraction level by using a formal base. This enables analysis before the application moves to the implementation phase. Different tools and frameworks supporting MoCs have been developed. Some of them can simulate the models and also verify their functionality and feasibility before the next design steps. In view of this, we present a novel method for analysis and identification of possible automation approaches applicable to embedded systems design flow supported by formal models of computation. A comprehensive case study shows the potential and applicability of our method11212

A Runtime Reconfiguration Design Targeting Avionics Systems

Real-time embedded systems are present in various application domains such as automotive, aeronautical, space, and telecommunications. Avionics systems (i.e., aviation electronics) represent a specialized class for the aerospace branch. It is a fact that avionics are getting more and more complex considering functionality and design and also using an increased number of digital computer resources. Besides the safety-critical aspect, performance and power consumption have also to be taken into consideration for new designs. Therefore, it is needed to adopt new system capabilities like runtime reconfiguration. In this context, modern system-on-chip (SoC) composed by heterogeneous hardware (i.e., microcontroller and field-programmable gate arrays - FPGA) can figure as an alternative solution. Then, reconfiguration is allowed to take place in runtime, which makes FPGA-based devices interesting for future avionics systems design. Considering this scenario, we introduce in this paper a runtime reconfiguration design implemented using a SoC. Basically, two different areas comprise the SoC hardware architecture: a hard processor area and a reconfigurable area. The former has the authority to manage which configuration will be programmed/used in a given time. The developed design enables both full and partial reconfiguration. In the research work results, we show how different kinds of configuration bitstream modes (i.e., and/or, scrub, scrub clear/set) and data compression impact the system's performance and power consumption. For instance, one full reconfiguration bitstream with no data compression takes similar to 29 ms to complete with average power consumption of similar to 42 mW. On the other hand, a given partial reconfiguration (and/or mode) takes similar to 2.73 ms to complete with similar to 22 mW average power consumption. Finally, our proposed design opens up the possibility to optimize a system towards adaptability to comply with real-time constraints changing regarding performance and power consumption.35th IEEE/AIAA Digital Avionics Systems Conference (DASC)SEP 25-29, 2016Sacramento, C

Modeling and simulation of dynamic applications using scenario-aware dataflow

The tradeoff between analyzability and expressiveness is a key factor when choosing a suitable dataflow model of computation (MoC) for designing, modeling, and simulating applications considering a formal base. A large number of techniques and analysis tools exist for static dataflow models, such as synchronous dataflow. However, they cannot express the dynamic behavior required for more dynamic applications in signal streaming or to model runtime reconfigurable systems. On the other hand, dynamic dataflow models like Kahn process networks sacrifice analyzability for expressiveness. Scenario-aware dataflow (SADF) is an excellent tradeoff providing sufficient expressiveness for dynamic systems, while still giving access to powerful analysis methods. In spite of an increasing interest in SADF methods, there is a lack of formally-defined functional models for describing and simulating SADF systems. This article overcomes the current situation by introducing a functional model for the SADF MoC, as well as a set of abstract operations for simulating it. We present the first modeling and simulation tool for SADF so far, implemented as an open source library in the functional framework ForSyDe. We demonstrate the capabilities of the functional model through a comprehensive tutorial-style example of a RISC processor described as an SADF application, and a traditional streaming application where we model an MPEG-4 simple profile decoder. We also present a couple of alternative approaches for functionally modeling SADF on different languages and paradigms. One of such approaches is used in a performance comparison with our functional model using the MPEG-4 simple profile decoder as a test case. As a result, our proposed model presented a good tradeoff between execution time and implementation succinctness. Finally, we discuss the potential of our formal model as a frontend for formal system design flows regarding dynamic applications245This research work was supported by the Swedish-Brazilian Research and Innovation Centre (CISB) and by Saab AB through the Call of Projects CISB Saab 04/2016